1. Field of the Invention
The present invention is generally directed to packaging techniques for electronic circuitry and in particular vertical stacking and interconnection techniques for a plurality of integrated circuits.
2. Description of Related Art Including Information Disclosed Under 37 CFR 1.97 and 1.98
Implantable medical devices for remedial treatment of and compensation for cardiac, neural and muscular deficiencies are known in the art. These devices range from cardiac pacemakers as described in U.S. Pat. No. 4,712,555 to Thornander, et al., to microstimulators as described in U.S. Pat. No. 6,208,894 to Schulman, et al. Also see R. Allan, “SIP Really Packs It In”, Electronic Design, Nov. 29, 2004, pp 45–54. The quest for minimization of such devices has provided, at least in the area of microstimulators, cylindrically shaped devices that range in size of about 6 mm in diameter and about 60 mm in axial length, see for example the device described in Schulman, et al., U.S. Pat. No. 6,315,721 ('721). The device described in '721 is configured so that, the electronics is packaged in a housing in tandem with a wire wound ferrite core used as a source of recharging energy for the device electronics power supply. Furthermore, the electronics themselves are arranged in a lengthwise fashion within the device, thereby adding to the overall length of the device. This configuration ultimately gives rise to the stated overall device length. In view of the implant nature of such medical devices, even still further device miniaturization would prove advantageous to device implantation and extraction as well as patient comfort.
Complex electronic devices typically require a large number of transistors, large enough that a single integrated circuit may not be able to perform all of the needed (or desired) functions. Such devices are typically fabricated from a plurality of integrated circuit chips that are then interconnected via a motherboard or the like, e.g., a hybrid circuit. While the use of flip chips and ball grid arrays (BGAs) are known for simplifying interconnection between the chips (along with wire bonds), such interconnection techniques can use up valuable and sometimes limited internal package volume. For example, U.S. Pat. Nos. 6,164,284; 6,185,452; 6,208,894; 6,315,721; 6,472,991; 6,564,807; and 6,667,923 and co-pending, commonly-assigned U.S. patent application Ser. Nos. 10/280,841 and 10/345,013 describe implantable medical devices and enclosed circuitry that are sized so that they are suitable for injection in a patient's body, i.e., being contained within an elongated housing having an axial dimension of less than 60 mm and a lateral dimension of less than 6 mm. With such limited outer dimensions and accordingly even smaller inner dimensions, the space available for needed circuitry is limited. Accordingly, various forms of stacking (sometimes referred to as 3D or vertical integration) techniques have been proposed. Such techniques require a frame (see for example Isaak, U.S. Pat. No. 6,404,043), interconnect paths at the edge of uniformly sized chips and/or carriers (see for example, Eide, U.S. Pat. No. 4,956,694), or additional vertical interconnect members and/or wire bond interconnects (see for example U.S. Pat. No. 6,133,626) to extend the assembly beyond two oppositely oriented flip chips, i.e., with one chip facing “up” and the other chip facing “down” so that their BGAs can mate together. It is believed that each of these techniques limit the use of valuable package volume.